ILP based don't care bits filling technique for reducing capture power

Abstract

Modern design for testability (DFT) techniques support the application of non-functional vectors with increased controllability, observability and ease of test generation complexity. High power demand due to excessive switching activity in test mode causes false failure, test escape and reliability issues. Therefore, generating power safe pattern test is an active research topic. Don't care bits present in the test set can be filled to minimize the capture power consumption due to delay test. In this paper, we formulate an optimization problem using integer linear programing. The proposed ILP based methodology is applicable for both launch-on-capture (LOC) and lunch-of-shift (LOS) schemes under minimization constraints for total capture switching activity reduction without any alteration in already existing automatic test pattern generation (ATPG) tools. Proposed formulation reduces peak weighted switching activity by 25% to 60% and average by 40% to 88% w.r.t randomly filled patterns.