Jaejune Jang, Kyuheon Cho, D. Jang, Minhwan Kim, Changjoon Yoon, Junsung Park, H.-S. Oh, Chiho Kim, Hyoungsoo Ko, Keunho Lee, Sangbae Yi
{"title":"Interdigitated LDMOS","authors":"Jaejune Jang, Kyuheon Cho, D. Jang, Minhwan Kim, Changjoon Yoon, Junsung Park, H.-S. Oh, Chiho Kim, Hyoungsoo Ko, Keunho Lee, Sangbae Yi","doi":"10.1109/ispsd.2013.6694462","DOIUrl":null,"url":null,"abstract":"Novel Interdigitated LDMOS is experimented resulting in best in class R<sub>SP</sub>-BV<sub>DSS</sub> performance (21.8mΩ-mm<sup>2</sup> with BV<sub>DSS</sub> of 47V) in comparison to published LDMOS. R<sub>SP</sub> improvement is made through additional current path by removing STI region in drift area. Breakdown voltage is maintained with lateral field plate effect from side of the current path. Proposed Interdigitated LDMOS satisfies reliability criteria (HCI, snap back) as 40V device. All of this is obtained without any process change.","PeriodicalId":175520,"journal":{"name":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ispsd.2013.6694462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
Novel Interdigitated LDMOS is experimented resulting in best in class RSP-BVDSS performance (21.8mΩ-mm2 with BVDSS of 47V) in comparison to published LDMOS. RSP improvement is made through additional current path by removing STI region in drift area. Breakdown voltage is maintained with lateral field plate effect from side of the current path. Proposed Interdigitated LDMOS satisfies reliability criteria (HCI, snap back) as 40V device. All of this is obtained without any process change.
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