Evaluation of gate oxide reliability in 3.3 kV 4H-SiC DMOSFET with J-Ramp TDDB methods

Abstract

In order to verify a gate oxide reliability of 3.3 kV 4H-SiC DMOS for rail car application, we developed a J-Ramp TDDB and a constant current stress screening method. We examined a conventional gate stack structure device with a single layer gate electrode and an improved one with double layered gate electrode; the latter one reveals a low hazard rate less than 1 FIT under a gate operation voltage of ±15 V at 150 °C.