FPGA-specific optimizations by partial function evaluation

Abstract

Partial evaluation is a common optimization technique in compiler design. It is also used in hardware synthesis for simplifying modules with constant signals. In this paper we introduce a new evaluation method for imperative programs in high-level synthesis, which benefits from control data, whose values do not vary in different program executions and are thus determinable in advance. The key aspect is to collect intermediate-results during evaluation which are then used for hardware-specific optimizations, such as constant folding, reduction of data-widths or elimination and parallelization of memory accesses. In case of memory intensive applications we are able to reduce the runtime of up to 20%.