High reliability and high performance 0.35 mu m gate-inverted TFT's for 16 Mbit SRAM applications using self-aligned LDD structures

Abstract

A simple self-aligned LDD structure is utilized in gate-inverted TFT's. The process is simple, and satisfactory reliability/uniformity is obtained. Consequently, the high performance devices are applicable to 16 Mbit SRAM's or beyond. We report on the following: fabrication of the devices integrated into our SRAM cells; the I-V characteristics of 0.35 mu m*0.35 mu m devices and their aging and temperature performance; a high I/sub ON//I/sub OFF/ ratio of 1.2*10/sup 8/ achieved without rapid thermal annealing or plasma hydrogenation; the uniformity of I/sub ON/; and considerations of device scaling and process margins.<>