Pub Date : 1997-10-25DOI: 10.1109/IEDM.1992.307433
T. Endoh, H. Iizuka, S. Aritome, R. Shirota, F. Masuoka
This paper describes the new write/erase operation methods in order to improve the read disturb characteristics for flash EEPROM cells which are written by channel hot electron injection and erased by F-N tunneling emission from the floating gate to the substrate. The new operation method is either applying a reverse polarity pulse after each erase pulse or applying a series of shorter erase pulses instead of a long single erase pulse. It is confirmed that by using the above operation method, the leakage current can be suppressed, and then the read disturb life time after 10/sup 5/ cycles W/E operation is more than 10 times longer in comparison with the conventional method.<>
{"title":"New write/erase operation technology for flash EEPROM cells to improve the read disturb characteristics","authors":"T. Endoh, H. Iizuka, S. Aritome, R. Shirota, F. Masuoka","doi":"10.1109/IEDM.1992.307433","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307433","url":null,"abstract":"This paper describes the new write/erase operation methods in order to improve the read disturb characteristics for flash EEPROM cells which are written by channel hot electron injection and erased by F-N tunneling emission from the floating gate to the substrate. The new operation method is either applying a reverse polarity pulse after each erase pulse or applying a series of shorter erase pulses instead of a long single erase pulse. It is confirmed that by using the above operation method, the leakage current can be suppressed, and then the read disturb life time after 10/sup 5/ cycles W/E operation is more than 10 times longer in comparison with the conventional method.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126765321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We report experimental measurements of the brightness of an electron beam produced by a ferroelectric cathode. The brightness value of B/sub n/ = 1.2x10/sup 1/1 A/m/sup 2/ rad/sup 2/ for a 15A, 1OkV beam exceeds that obtained from thermionic cathodes operating at comparable voltages. To our knowledge, these are the first reported measurements of the beam quality (emittance and brightness) of the electron beam from a ferroelectric cathode.<>
{"title":"A high brightness electron beam produced by a ferroelectric cathode","authors":"George Kirkman, B. Jiang, Nicholas Reinhardt","doi":"10.1063/1.113855","DOIUrl":"https://doi.org/10.1063/1.113855","url":null,"abstract":"We report experimental measurements of the brightness of an electron beam produced by a ferroelectric cathode. The brightness value of B/sub n/ = 1.2x10/sup 1/1 A/m/sup 2/ rad/sup 2/ for a 15A, 1OkV beam exceeds that obtained from thermionic cathodes operating at comparable voltages. To our knowledge, these are the first reported measurements of the beam quality (emittance and brightness) of the electron beam from a ferroelectric cathode.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126968489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-11-25DOI: 10.1109/IEDM.1992.307416
T. Ohzone, H. Iwata, Y. Uraoka, S. Odanaka
A two-dimensional (2-D) photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices is described. Photoemission-intensity profiles and photon-energy distributions can be measured in spatial resolution of 0.1 mu m. This technology reveals the 2-D edge effect of photoemission-intensity depending on isolation technology. The significant difference of photoemission characteristics is observed in LOCOS- and trench-isolated n-MOSFETs.<>
{"title":"A two-dimensional analysis of hot-carrier photoemission from LOCOS- and trench-isolated MOSFETs","authors":"T. Ohzone, H. Iwata, Y. Uraoka, S. Odanaka","doi":"10.1109/IEDM.1992.307416","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307416","url":null,"abstract":"A two-dimensional (2-D) photoemission analysis of hot-carrier effects in LOCOS- and trench-isolated CMOS devices is described. Photoemission-intensity profiles and photon-energy distributions can be measured in spatial resolution of 0.1 mu m. This technology reveals the 2-D edge effect of photoemission-intensity depending on isolation technology. The significant difference of photoemission characteristics is observed in LOCOS- and trench-isolated n-MOSFETs.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116016764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-08-08DOI: 10.1109/IEDM.1992.307307
C. Pierrat, A. Wong, S. Vaidya
The impact of phase-shifting mask topography on wafer exposure was studied via simulations and experimentation using phase-shifting masks fabricated by etching the quartz to define the shifted areas. The influence of the refractive index of the chromium layer and of the profile of the chromium patterns was shown to be minimal. On the other hand, the quartz profiles have a large impact on the wafer results. For vertical quartz profiles, the intensity of the light going through the etched portion of the mask is lower than that going through the unetched portion of the mask and varies with feature size. This problem can be addressed either by optimizing the quartz profiles or by biasing the size of the features depending on the type of pattern.<>
{"title":"Phase-shifting mask topography effects on lithographic image quality","authors":"C. Pierrat, A. Wong, S. Vaidya","doi":"10.1109/IEDM.1992.307307","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307307","url":null,"abstract":"The impact of phase-shifting mask topography on wafer exposure was studied via simulations and experimentation using phase-shifting masks fabricated by etching the quartz to define the shifted areas. The influence of the refractive index of the chromium layer and of the profile of the chromium patterns was shown to be minimal. On the other hand, the quartz profiles have a large impact on the wafer results. For vertical quartz profiles, the intensity of the light going through the etched portion of the mask is lower than that going through the unetched portion of the mask and varies with feature size. This problem can be addressed either by optimizing the quartz profiles or by biasing the size of the features depending on the type of pattern.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117279399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-12-13DOI: 10.1109/IEDM.1992.307363
M. Suzuki, T. Homma, H. Koga, T. Tanigawa, Y. Murao
A new interlayer dielectric film planarization technology for sub-half-micron multilevel interconnections has been developed. This technology utilizes a new selective TEOS-Ozone APCVD SiO/sub 2/ film formation technique which can be realized by differences in surface adsorption properties and flow characteristics of siloxane oligomers. The deposition rate can be reduced by putting Ti or its alloy metal films such as TiN and TiW on top of Al wirings. These metal films can reduce the oligomer adsorption and assist the oligomer flow into the spacings between Al wirings. Furthermore, the selectivity is enhanced by a CF/sub 4/ gas plasma pre-treatment, even on top of the W films. The TEOS-Ozone APCVD SiO/sub 2/ films deposited on the Ti/Al, TiN/Al, TiW/Al or W/Al wirings with the CF/sub 4/ pre-treatment were more than 40% thinner than those on PECVD SiO/sub 2/ under-layers. Higher capability for both local and global planarization of interlayer dielectrics was confirmed in a multilevel metallization scheme in the double-level Al interconnection technology with the 0.6 mu m design rule and in a prototype 64M DRAM fabrications.<>
{"title":"A fully planarized multilevel interconnection technology using selective TEOS-Ozone APCVD","authors":"M. Suzuki, T. Homma, H. Koga, T. Tanigawa, Y. Murao","doi":"10.1109/IEDM.1992.307363","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307363","url":null,"abstract":"A new interlayer dielectric film planarization technology for sub-half-micron multilevel interconnections has been developed. This technology utilizes a new selective TEOS-Ozone APCVD SiO/sub 2/ film formation technique which can be realized by differences in surface adsorption properties and flow characteristics of siloxane oligomers. The deposition rate can be reduced by putting Ti or its alloy metal films such as TiN and TiW on top of Al wirings. These metal films can reduce the oligomer adsorption and assist the oligomer flow into the spacings between Al wirings. Furthermore, the selectivity is enhanced by a CF/sub 4/ gas plasma pre-treatment, even on top of the W films. The TEOS-Ozone APCVD SiO/sub 2/ films deposited on the Ti/Al, TiN/Al, TiW/Al or W/Al wirings with the CF/sub 4/ pre-treatment were more than 40% thinner than those on PECVD SiO/sub 2/ under-layers. Higher capability for both local and global planarization of interlayer dielectrics was confirmed in a multilevel metallization scheme in the double-level Al interconnection technology with the 0.6 mu m design rule and in a prototype 64M DRAM fabrications.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116690764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-12-01DOI: 10.1109/IEDM.1992.307366
K. Ueno, K. Ohto, K. Tsunenari, K. Kajiyana, K. Kikuta, T. Kikkawa
In order to realize minimum pitch interconnections without degrading reliability, self-aligned contacts (SACs) between interconnections and plugs are necessary. The planarized interconnections with SAC plugs is formed for quarter-micron size as follows. Interconnection trenches and contact holes are formed using a self-aligned etch-stop layer, followed by simultaneous metal-filling into the trenches and contact holes. Si-rich oxide (SRO) films are found to be promising for a self-aligned etch-stop layer with their high etching selectivity to SiO/sub 2/ as high as 10-30. Sufficiently low line resistance of 15 k Omega /cm and low contact resistance of 70 Omega /contact are obtained with the quarter-micron W-interconnection with the SAC plugs.<>
为了在不降低可靠性的前提下实现最小间距互连，需要在互连和插头之间使用自对准触点(SACs)。与SAC插头的平面互连的尺寸为四分之一微米，形成如下。使用自对准蚀刻停止层形成互连沟槽和接触孔，然后同时将金属填充到沟槽和接触孔中。富硅氧化物(SRO)薄膜对SiO/ sub2 /的高蚀刻选择性高达10-30，有望成为自对准刻蚀停止层。与SAC插头的四分之一微米w互连获得了15 k ω /cm的足够低的线路电阻和70 ω /触点的低接触电阻
{"title":"A quarter-micron planarized interconnection technology with self-aligned plug","authors":"K. Ueno, K. Ohto, K. Tsunenari, K. Kajiyana, K. Kikuta, T. Kikkawa","doi":"10.1109/IEDM.1992.307366","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307366","url":null,"abstract":"In order to realize minimum pitch interconnections without degrading reliability, self-aligned contacts (SACs) between interconnections and plugs are necessary. The planarized interconnections with SAC plugs is formed for quarter-micron size as follows. Interconnection trenches and contact holes are formed using a self-aligned etch-stop layer, followed by simultaneous metal-filling into the trenches and contact holes. Si-rich oxide (SRO) films are found to be promising for a self-aligned etch-stop layer with their high etching selectivity to SiO/sub 2/ as high as 10-30. Sufficiently low line resistance of 15 k Omega /cm and low contact resistance of 70 Omega /contact are obtained with the quarter-micron W-interconnection with the SAC plugs.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128630212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-10-14DOI: 10.1109/IEDM.1992.307400
S. Luning, P. Rousseau, P. Griffin, P. Carey, J. Plummer
This work investigates the kinetics of arsenic deactivation at temperatures from 500 to 800 degrees C and for concentrations between 1*10/sup 20/ and 1*10/sup 21//cm/sup 3/. Using profiles created by repeated laser melt annealing, we determine mobility as a function of both active and inactive dopant concentration and then characterize the dynamics of carrier deactivation. We observe retrograde resistivity versus concentration at high doses, which is explained by a mobility reduction due to the inactive arsenic and by retrograde electrical activity of the dopant itself.<>
{"title":"Kinetics of high concentration arsenic deactivation at moderate to low temperatures","authors":"S. Luning, P. Rousseau, P. Griffin, P. Carey, J. Plummer","doi":"10.1109/IEDM.1992.307400","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307400","url":null,"abstract":"This work investigates the kinetics of arsenic deactivation at temperatures from 500 to 800 degrees C and for concentrations between 1*10/sup 20/ and 1*10/sup 21//cm/sup 3/. Using profiles created by repeated laser melt annealing, we determine mobility as a function of both active and inactive dopant concentration and then characterize the dynamics of carrier deactivation. We observe retrograde resistivity versus concentration at high doses, which is explained by a mobility reduction due to the inactive arsenic and by retrograde electrical activity of the dopant itself.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123808427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-05-25DOI: 10.1109/IEDM.1992.307343
Q. Wang, D. Mcdermott, C. Kou, A. T. Lin, K. Chu, N. Luhmann, J. Pretterebner
An extremely high power three-section second-harmonic 35 GHz gyro-TWT has been designed with a self-consistent nonlinear simulation code (1). An output power of 530 kW with 21% efficiency, 54 dB gain and 6% bandwidth is predicted. To substantiate the claim that a harmonic gyro-TWT can generate significantly higher output power with better stability than fundamental gyro-TWTs due to the higher beam currents allowed for the weaker harmonic interaction, a proof-of-principle Ku-band experiment is being constructed at UCLA with comparable performance predicted. A single anode 100 kV, 20 A MIG is being built to generate the alpha = upsilon /sub perpendicular to // upsilon /sub ///=1 electron beam with Delta upsilon /sub //// upsilon /sub ///=8%.<>
{"title":"High-power second harmonic gyro-TWT amplifier","authors":"Q. Wang, D. Mcdermott, C. Kou, A. T. Lin, K. Chu, N. Luhmann, J. Pretterebner","doi":"10.1109/IEDM.1992.307343","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307343","url":null,"abstract":"An extremely high power three-section second-harmonic 35 GHz gyro-TWT has been designed with a self-consistent nonlinear simulation code (1). An output power of 530 kW with 21% efficiency, 54 dB gain and 6% bandwidth is predicted. To substantiate the claim that a harmonic gyro-TWT can generate significantly higher output power with better stability than fundamental gyro-TWTs due to the higher beam currents allowed for the weaker harmonic interaction, a proof-of-principle Ku-band experiment is being constructed at UCLA with comparable performance predicted. A single anode 100 kV, 20 A MIG is being built to generate the alpha = upsilon /sub perpendicular to // upsilon /sub ///=1 electron beam with Delta upsilon /sub //// upsilon /sub ///=8%.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126269894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307356
P. Fazan, V. K. Mathews, N. Sandler, G. Lo, D. Kwong
Storage capacitors integrating ultrathin chemical vapor deposited-Ta/sub 2/O/sub 5/ (10 to 15 nm thick) on rapid thermal nitrided rugged polycrystalline silicon electrodes are proposed for 256 Mb stacked dynamic random access memory applications. The unique combination of this high dielectric constant material with a rugged hemispherical grain silicon electrode allows the manufacture of the ultra high capacitance (20.4 fF/ mu m/sup 2/) stacked structures needed beyond 64 Mb.<>
在快速热氮化坚固多晶硅电极上集成超薄化学气相沉积- ta /sub 2/O/sub 5/ (10 ~ 15nm厚)的存储电容器可用于256mb堆叠动态随机存取存储器应用。这种高介电常数材料与坚固的半球形颗粒硅电极的独特组合允许制造超过64 Mb所需的超高电容(20.4 fF/ mu m/sup 2/)堆叠结构。
{"title":"A high-C capacitor (20.4 fF/ mu m/sup 2/) with ultrathin CVD-Ta/sub 2/O/sub 5/ films deposited on rugged poly-Si for high density DRAMs","authors":"P. Fazan, V. K. Mathews, N. Sandler, G. Lo, D. Kwong","doi":"10.1109/IEDM.1992.307356","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307356","url":null,"abstract":"Storage capacitors integrating ultrathin chemical vapor deposited-Ta/sub 2/O/sub 5/ (10 to 15 nm thick) on rapid thermal nitrided rugged polycrystalline silicon electrodes are proposed for 256 Mb stacked dynamic random access memory applications. The unique combination of this high dielectric constant material with a rugged hemispherical grain silicon electrode allows the manufacture of the ultra high capacitance (20.4 fF/ mu m/sup 2/) stacked structures needed beyond 64 Mb.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114983964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1992.307369
M. Kao, S. Fu, P. Ho, P. Smith, P. Chao, K. Nordheden, Sujane C. Wang
This paper reports the development of double recessed pseudomorphic GaAs High Electron Mobility Transistors (HEMTs) for high voltage operation. The GaAs-based power HEMT with 0.25 mu m gate-length exhibited a gate to drain breakdown voltage of 30 volts, a peak g/sub m/ of 510 mS/mm, and a maximum current density of 540 mA/mm. When biased to 14 volts on the drain, the 400 mu m wide HEMT delivered 505 mW (1.26 W/mm) output power at 4.5 GHz. This is the highest output power density and drain-source operating voltage ever reported for HEMT devices. The device also showed excellent 4.5 and 10 GHz power performance combination (power gain, power density, power-added efficiency) at V/sub ds/=8V. The significant extension of device drain bias range as well as increase in the product of current density and breakdown voltage were attributed to the adoption of channel recess using reactive ion etching.<>
{"title":"Very high voltage AlGaAs/InGaAs pseudomorphic power HEMTs","authors":"M. Kao, S. Fu, P. Ho, P. Smith, P. Chao, K. Nordheden, Sujane C. Wang","doi":"10.1109/IEDM.1992.307369","DOIUrl":"https://doi.org/10.1109/IEDM.1992.307369","url":null,"abstract":"This paper reports the development of double recessed pseudomorphic GaAs High Electron Mobility Transistors (HEMTs) for high voltage operation. The GaAs-based power HEMT with 0.25 mu m gate-length exhibited a gate to drain breakdown voltage of 30 volts, a peak g/sub m/ of 510 mS/mm, and a maximum current density of 540 mA/mm. When biased to 14 volts on the drain, the 400 mu m wide HEMT delivered 505 mW (1.26 W/mm) output power at 4.5 GHz. This is the highest output power density and drain-source operating voltage ever reported for HEMT devices. The device also showed excellent 4.5 and 10 GHz power performance combination (power gain, power density, power-added efficiency) at V/sub ds/=8V. The significant extension of device drain bias range as well as increase in the product of current density and breakdown voltage were attributed to the adoption of channel recess using reactive ion etching.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114655462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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