Robust the ESD Reliability by Drain-side Super-junctions for the UHV Circular nLDMOS

Shen-Li Chen, Pei-Lin Wu, Y. Jhou, Po-Lin Lin, Sheng-Kai Fan
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Abstract

In this paper, 300 V circular nLDMOS DUTs is used as the experimental benchmark group, and a smart architecture of HVPW is added into the HVNW drift-region to form a super-junction (SJ) structure (radial-type SJ). And then, for the HVPW/HVNW area modulation of radial-type SJ, three different kinds of area ratios is fabricated. However, the HBM capacity of this nLDMOS reference group has only 2500V. Furthermore, as for the radial-type SJ and HVPW/HVNW with different proportions of area modulation in the drift region, it has the highest HBM-immunity capacity of 7000V when the HVPW/HVNW area ratio of 2 to 1. That is to say, in the SJ architecture, the higher the proportion of HVPW/HVNW, the stronger its ESD immunity reliability.
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超高压环形nLDMOS漏极侧超级结的防静电可靠性研究
本文以300 V圆形nLDMOS DUTs作为实验基准组,在HVPW漂移区加入HVPW的智能架构,形成超结(SJ)结构(径向型SJ)。然后,针对径向型SJ的HVPW/HVNW面积调制,制备了三种不同的面积比。然而,该nLDMOS参考组的HBM容量只有2500V。此外,对于径向型SJ和漂移区不同面积调制比例的HVPW/HVNW,当HVPW/HVNW面积比为2比1时,其抗hbm能力最高,为7000V。也就是说,在SJ架构中,HVPW/ hnvw比例越高,其抗静电可靠性越强。
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