Physical-Based SPICE Model of CMOS STI y-Stress Effect

Abstract

In this paper, we proposed a new physical-based equation to model the CMOS transistor STI y-stress (in the direction of channel width). It can be used in any SPICE MOS model and it has been verified on 0.13 um CMOS transistors. The physical characteristics of the compressive STI y-stress effect on saturation drain current, Idsat are captured by using a new proposed transistor layout method. The equation that is able to describe the physical characteristics of the STI y-stress effect is incorporated into the electron and hole mobility, uO of the SPICE model to capture the y-stress effect on Idsat. With the combination of the new y-stress parameters and the default delta width parameters in the SPICE model, we are able to fit the simulation curve to the hook shaped Idsat curve from the actual silicon data.