Pub Date : 2006-12-01DOI: 10.1109/SMELEC.2006.380785
Z. Feng, L. Cheng, Chu-Wan Huang, Ying-Lang Wang, T. Yang
Synchrotron radiation X-ray diffraction and X-ray photoelectron spectroscopy techniques have been employed for the investigation on Si-based layer structures for sub-micron Si-IC Applications. The high energy synchrotron radiation light sources have produced plenty of X-ray lines with high index diffraction and strong X-ray photoelectron emissions. The useful information will increase our understanding of these materials which are applied extensively to the semiconductor industry.
{"title":"Synchrotron Radiation X-ray Diffraction and X-ray Photoelectron Spectroscopy Investigation on Si-based Structures for Sub-Micron Si-IC Applications","authors":"Z. Feng, L. Cheng, Chu-Wan Huang, Ying-Lang Wang, T. Yang","doi":"10.1109/SMELEC.2006.380785","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380785","url":null,"abstract":"Synchrotron radiation X-ray diffraction and X-ray photoelectron spectroscopy techniques have been employed for the investigation on Si-based layer structures for sub-micron Si-IC Applications. The high energy synchrotron radiation light sources have produced plenty of X-ray lines with high index diffraction and strong X-ray photoelectron emissions. The useful information will increase our understanding of these materials which are applied extensively to the semiconductor industry.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126875747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/SMELEC.2006.380770
T. C. Hong, R. Ismail
The evolution of metal-oxide-semiconductor field effect transistor (MOSFET) technology has been governed mainly by device scaling over the past twenty years. One of the key questions concerning future ULSI technology is whether MOSFET devices can be scaled to 100 nmchannel length and beyond for continuing density and performance improvement. In this paper, the design, fabrication and characterization of high-performance and low-power 90 nm channel length MOSFET devices are described. Several parameters have to be scaled down such as gate oxide thickness, channel length, ion implantation for threshold voltage adjustment and other specifications to achieve desirable electrical characteristic. To control the short-channel effect (SCE) and hot-carrier reliability that limits device scaling, lightly doped drain (LDD) structure, shallow junction of drain / source and Shallow Trench Isolation (STI) are implemented. Virtual wafer fabrication (VWF) Silvaco TCAD Tools is used for fabrication and simulation of CMOS transistor namely ATHENA and ATLAS. Simulations using these programs provided the opportunity to study the effect of different device parameters on the overall device performance. The devices were simulated and gradually the performance of each one was improved, until an optimal device configuration was created for a particular application.
{"title":"Device Design Consideration for Nanoscale MOSFET Using Semiconductor TCAD Tools","authors":"T. C. Hong, R. Ismail","doi":"10.1109/SMELEC.2006.380770","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380770","url":null,"abstract":"The evolution of metal-oxide-semiconductor field effect transistor (MOSFET) technology has been governed mainly by device scaling over the past twenty years. One of the key questions concerning future ULSI technology is whether MOSFET devices can be scaled to 100 nmchannel length and beyond for continuing density and performance improvement. In this paper, the design, fabrication and characterization of high-performance and low-power 90 nm channel length MOSFET devices are described. Several parameters have to be scaled down such as gate oxide thickness, channel length, ion implantation for threshold voltage adjustment and other specifications to achieve desirable electrical characteristic. To control the short-channel effect (SCE) and hot-carrier reliability that limits device scaling, lightly doped drain (LDD) structure, shallow junction of drain / source and Shallow Trench Isolation (STI) are implemented. Virtual wafer fabrication (VWF) Silvaco TCAD Tools is used for fabrication and simulation of CMOS transistor namely ATHENA and ATLAS. Simulations using these programs provided the opportunity to study the effect of different device parameters on the overall device performance. The devices were simulated and gradually the performance of each one was improved, until an optimal device configuration was created for a particular application.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128900057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381062
Sukirno, S. Z. Bisri, Irmelia, L. Hasanah, A. B. Suryamas, I. Usman, Mursal
Carbon nanotubes research is one of the top five hot research topics in physics. It is because of its unique properties and functionalities, which leads to wide-range applications. One of the most interesting potential applications is in term of nanoelectronic device. There is a possibility to found some unique structure, where different carbon nanotubes are connected coaxially. It has been modeled carbon nanotubes heterojunction, which was built from two different carbon nanotubes, that one is metallic and the other one is semiconducting. There are two different carbon nanotubes metal-semiconductor heterojunction. The first one is built from CNT (10,10) as metallic carbon nanotube and CNT (17,0) as semiconductor carbon nanotube. The other one is built from CNT (5,5) as metallic carbon nanotube and CNT (8,0). All of the semiconducting carbon nanotubes are assumed to be a pyridine-like N-doped. Those two heterojunctions are different in term of their structural shape and diameter. It has been calculated their charge distribution and potential profile, which would be useful for the simulation of their electronic transport properties. The calculations are performed by using self-consistent method to solve non-homogeneous Poisson's equation with aid of universal density of states calculation method for carbon nanotubes. The calculations are done by varying the doping fraction of the semiconductor carbon nanotubes. It is obtained that the charge are distributed almost evenly along the semiconducting carbon nanotubes and the potential profile peaks in the vincinity of semiconducting carbon nanotubes center position, with some valley-shapes that show some sign of charge confinements nearby. However, from the comparison of two different heterojunctions, it could be inferred that the geometrical aspects of the heterojunction building blocks has effect on their electronic transport parameter. It is also obtained the calculation results of the electron tunneling transmission coefficient that transported through the heterojunction, which has energy lower than the potential barrier value.
{"title":"Comparison of Electronic Transport Parameter of CNT(10,10)/CNT(17,0) and CNT(5,5)/CNT(8,0) Carbon Nanotube Metal-Semiconductor On-Tube Heterojunction","authors":"Sukirno, S. Z. Bisri, Irmelia, L. Hasanah, A. B. Suryamas, I. Usman, Mursal","doi":"10.1109/SMELEC.2006.381062","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381062","url":null,"abstract":"Carbon nanotubes research is one of the top five hot research topics in physics. It is because of its unique properties and functionalities, which leads to wide-range applications. One of the most interesting potential applications is in term of nanoelectronic device. There is a possibility to found some unique structure, where different carbon nanotubes are connected coaxially. It has been modeled carbon nanotubes heterojunction, which was built from two different carbon nanotubes, that one is metallic and the other one is semiconducting. There are two different carbon nanotubes metal-semiconductor heterojunction. The first one is built from CNT (10,10) as metallic carbon nanotube and CNT (17,0) as semiconductor carbon nanotube. The other one is built from CNT (5,5) as metallic carbon nanotube and CNT (8,0). All of the semiconducting carbon nanotubes are assumed to be a pyridine-like N-doped. Those two heterojunctions are different in term of their structural shape and diameter. It has been calculated their charge distribution and potential profile, which would be useful for the simulation of their electronic transport properties. The calculations are performed by using self-consistent method to solve non-homogeneous Poisson's equation with aid of universal density of states calculation method for carbon nanotubes. The calculations are done by varying the doping fraction of the semiconductor carbon nanotubes. It is obtained that the charge are distributed almost evenly along the semiconducting carbon nanotubes and the potential profile peaks in the vincinity of semiconducting carbon nanotubes center position, with some valley-shapes that show some sign of charge confinements nearby. However, from the comparison of two different heterojunctions, it could be inferred that the geometrical aspects of the heterojunction building blocks has effect on their electronic transport parameter. It is also obtained the calculation results of the electron tunneling transmission coefficient that transported through the heterojunction, which has energy lower than the potential barrier value.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115491809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381099
L. S. Chuah, C. W. Chin, Z. Hassan, H. A. Hassan
Porous SiO2 can be used as a template to reduce substrate-induced stress, similar to porous GaN. Such a regrowth method may reduce the defect density in the epitaxial layer leading to high quality stress free layer on porous template. The samples were prepared on silicon (Si) wafers, (111)-oriented, with n- doping. After standard cleaning steps, SiO2 of 1200 Aring thickness was prepared by thermal oxidation of the Si at 1000deg C for 1.50 hours. The wafer was then cleaved into few pieces. To prepare porous structures by photoelectrochemical (PEC) method, the samples were dipped into a mixture of hydrofluoric acid (HF): water: ethanol under different etching durations. Structural properties of porous SiO2 have been investigated by scanning electron microscope (SEM). Elemental composition of the sample was identified using energy dispersive X-ray (EDX) analysis. Fourier transform infrared reflectance (FTIR) spectroscopy was used to characterize the chemical species and chemical bonding state.
{"title":"Porous Silicon Dioxide Synthesized using Photoelectrochemical (PEC) Wet Etching","authors":"L. S. Chuah, C. W. Chin, Z. Hassan, H. A. Hassan","doi":"10.1109/SMELEC.2006.381099","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381099","url":null,"abstract":"Porous SiO2 can be used as a template to reduce substrate-induced stress, similar to porous GaN. Such a regrowth method may reduce the defect density in the epitaxial layer leading to high quality stress free layer on porous template. The samples were prepared on silicon (Si) wafers, (111)-oriented, with n- doping. After standard cleaning steps, SiO2 of 1200 Aring thickness was prepared by thermal oxidation of the Si at 1000deg C for 1.50 hours. The wafer was then cleaved into few pieces. To prepare porous structures by photoelectrochemical (PEC) method, the samples were dipped into a mixture of hydrofluoric acid (HF): water: ethanol under different etching durations. Structural properties of porous SiO2 have been investigated by scanning electron microscope (SEM). Elemental composition of the sample was identified using energy dispersive X-ray (EDX) analysis. Fourier transform infrared reflectance (FTIR) spectroscopy was used to characterize the chemical species and chemical bonding state.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115693566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381042
M. Mehrban, S. Kouravand, G. Rezazadeh, A. Donyavi
In this paper sensitivity of MEMS capacitive thermal sensors based on deflection of a bimetallic cantilever beam was investigated. Using design of experiment method, and applying a 25 factorial design the effect of factors in this sensor was calculated and main factors that affect on sensor's sensitivity were identified. Analysis of variance for the main factors of design and their interactions were studied for their significance.
{"title":"Application of Full Factorial Design Method in MEMS Capacitive Thermal Sensor Sensitivity","authors":"M. Mehrban, S. Kouravand, G. Rezazadeh, A. Donyavi","doi":"10.1109/SMELEC.2006.381042","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381042","url":null,"abstract":"In this paper sensitivity of MEMS capacitive thermal sensors based on deflection of a bimetallic cantilever beam was investigated. Using design of experiment method, and applying a 25 factorial design the effect of factors in this sensor was calculated and main factors that affect on sensor's sensitivity were identified. Analysis of variance for the main factors of design and their interactions were studied for their significance.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124272111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381061
H. T. Su, I. Llamas-Garro, M. Lancaster, M. Prest, Jaehyoung Park, Jung-Mu Kim, C. Baek, Yong-Kweon Kim
The performance of micro-electro-mechanical system (MEMS) metal switches were investigated at wide temperature range. Measurements were carried out using cryogenic probe station and S-parameters were taken using a network analyser for frequencies up to 20 GHz. A total of 28 switches were evaluated. The investigation shows a 50% increase in the actuation voltage and a decrease in the percentage of operational switches as the temperature was reduced to 10 K. At room temperature the best isolation (when open) was 30 dB at 10 GHz with an insertion loss of 0.14 dB (when closed). Measurement accuracy was reduced at low temperature, however, isolations and insertion losses were similar to room temperature values.
{"title":"Investigating the Performance of RF MEMS Switches","authors":"H. T. Su, I. Llamas-Garro, M. Lancaster, M. Prest, Jaehyoung Park, Jung-Mu Kim, C. Baek, Yong-Kweon Kim","doi":"10.1109/SMELEC.2006.381061","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381061","url":null,"abstract":"The performance of micro-electro-mechanical system (MEMS) metal switches were investigated at wide temperature range. Measurements were carried out using cryogenic probe station and S-parameters were taken using a network analyser for frequencies up to 20 GHz. A total of 28 switches were evaluated. The investigation shows a 50% increase in the actuation voltage and a decrease in the percentage of operational switches as the temperature was reduced to 10 K. At room temperature the best isolation (when open) was 30 dB at 10 GHz with an insertion loss of 0.14 dB (when closed). Measurement accuracy was reduced at low temperature, however, isolations and insertion losses were similar to room temperature values.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120848168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.381044
M. Nabipoor, B. Majlis
A visual method is demonstrated for fabrication of silicon membranes by deep reactive ion etching (DRIE) and wet etching techniques. A DRIE cavity is created on silicon substrate closed to the membrane recess, and the backside of the wafer is etched by a wet etching process until it reaches the bottom of the DRIE cavity. Both isotropic and anisotropic wet etching with a loose control of temperature and concentration could be used. Because of the high accuracy etch rate of the silicon by DRIE, the depth of the cavity could be defined accurately and the fabricated membrane thickness would be precise.
{"title":"High-Precision Thickness Control of Silicon Membranes Using Etching Techniques","authors":"M. Nabipoor, B. Majlis","doi":"10.1109/SMELEC.2006.381044","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.381044","url":null,"abstract":"A visual method is demonstrated for fabrication of silicon membranes by deep reactive ion etching (DRIE) and wet etching techniques. A DRIE cavity is created on silicon substrate closed to the membrane recess, and the backside of the wafer is etched by a wet etching process until it reaches the bottom of the DRIE cavity. Both isotropic and anisotropic wet etching with a loose control of temperature and concentration could be used. Because of the high accuracy etch rate of the silicon by DRIE, the depth of the cavity could be defined accurately and the fabricated membrane thickness would be precise.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127487671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380753
M.S. Islam, M.S. Zaman Sarker, K.A. Ahmed Rafi, M. Othman
The goal of this paper is to develop an algorithm of fuzzy logic controller (FLC) for automatic air-condition controlling system. The fuzzy logic system is used to design this algorithm. Two inputs and one output are designed with an industrial application in mind. This system consists of two sensors for feedback control: one to the monitor of temperature and another one to the monitor of humidity. There are three control elements: cooling valve, heating valve, and humidifying valve, to adjust the temperature and humidity of the air supply. Fuzzy rules are formulated by temperature and humidity. The model of this controller algorithm has been simulated using MATLAB simulation. Finally, the developed algorithm has been designed for implementing the hardware VLSI chip using VHDL language from EDA tools.
{"title":"Development of a Fuzzy Logic Controller Algorithm for Air-conditioning System","authors":"M.S. Islam, M.S. Zaman Sarker, K.A. Ahmed Rafi, M. Othman","doi":"10.1109/SMELEC.2006.380753","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380753","url":null,"abstract":"The goal of this paper is to develop an algorithm of fuzzy logic controller (FLC) for automatic air-condition controlling system. The fuzzy logic system is used to design this algorithm. Two inputs and one output are designed with an industrial application in mind. This system consists of two sensors for feedback control: one to the monitor of temperature and another one to the monitor of humidity. There are three control elements: cooling valve, heating valve, and humidifying valve, to adjust the temperature and humidity of the air supply. Fuzzy rules are formulated by temperature and humidity. The model of this controller algorithm has been simulated using MATLAB simulation. Finally, the developed algorithm has been designed for implementing the hardware VLSI chip using VHDL language from EDA tools.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124936138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380720
Mo Zhi-qiang, G. Dong, H. Younan, Z. Siping, Xing Zhenxiang
Airborne boron and phosphorus contaminations on wafer surface has been analysed by TOF-SIMS. A known boron and phosphorus concentration BPSG sample was used as reference for the calibration of the TOF-SIMS. The detection limit reaches 1E8 at/cm2 for boron and 1E10 at/cm2 for phosphorus. This method is easy to applied and no sample preparation required. So TOF- SIMS is a very good monitoring technique for airborne boron and phosphorus on wafer surface.
{"title":"Analysis of Airborne Boron and Phosphorus Contaminations on Wafer Surface by TOF-SIMS","authors":"Mo Zhi-qiang, G. Dong, H. Younan, Z. Siping, Xing Zhenxiang","doi":"10.1109/SMELEC.2006.380720","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380720","url":null,"abstract":"Airborne boron and phosphorus contaminations on wafer surface has been analysed by TOF-SIMS. A known boron and phosphorus concentration BPSG sample was used as reference for the calibration of the TOF-SIMS. The detection limit reaches 1E8 at/cm2 for boron and 1E10 at/cm2 for phosphorus. This method is easy to applied and no sample preparation required. So TOF- SIMS is a very good monitoring technique for airborne boron and phosphorus on wafer surface.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122568865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-11-01DOI: 10.1109/SMELEC.2006.380687
Z. Siping, H. Younan, Mo Zhi-qiang, Cho Jie Ying
To identify nitride from oxide layer on the trench, it is necessary to perform BOE chemical staining. However, chemical staining using BOE will damage the oxide layer, causing inaccurate readings in the oxide gauging measurement in the trench. Moreover, damage on the oxide layer caused heavy charging at the side of the trench and the surface of oxide layer. In this paper, we proposed to coat a Cr layer over the trench before chemical staining. The damage problem was eliminated and the measurement of oxide gauging was more accurate. A application case is discussed for trench TEOS gauging measurement.
{"title":"Studies on A Sample Preparation Method for HR-SEM and Application in Failure Analysis of Trench TEOS Gauging Measurement in Wafer Fabrication","authors":"Z. Siping, H. Younan, Mo Zhi-qiang, Cho Jie Ying","doi":"10.1109/SMELEC.2006.380687","DOIUrl":"https://doi.org/10.1109/SMELEC.2006.380687","url":null,"abstract":"To identify nitride from oxide layer on the trench, it is necessary to perform BOE chemical staining. However, chemical staining using BOE will damage the oxide layer, causing inaccurate readings in the oxide gauging measurement in the trench. Moreover, damage on the oxide layer caused heavy charging at the side of the trench and the surface of oxide layer. In this paper, we proposed to coat a Cr layer over the trench before chemical staining. The damage problem was eliminated and the measurement of oxide gauging was more accurate. A application case is discussed for trench TEOS gauging measurement.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117102779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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