High speed analog-to-digital converter design verification tests in satellite receivers

Abstract

High-speed analog-to-digital converter using on-chip digital de-multiplexing and clock distribution is presented with detail sequences of operation for dynamic performance testing. Digital outputs are post processed and fed into a computer-aided ADC performance characterization tool. The problems of high sampling rate ADC testing are described. The test methodologies described reduce test costs and overcome many test hardware limitations. As our focus is on satellite receiver systems, we emphasize the measurement of inter-modulation distortion and effective resolution bandwidth. As a primary characterization component, Fourier analysis is used and we address the issue of sample window adjustment to eliminate spectral leakage and false spur generation. A 6-bit 800 MSa/s dual channel SiGe-based ADC from Hughes network systems is used as a target example.