Mandovi Mukherjee, N. M. Rahman, Coleman DeLude, J. Driscoll, Uday Kamal, J. Woo, Jamin Seo, Sudarshan Sharma, Xiangyu Mao, Payman Behnam, Sharjeel Khan, D. Kim, Jianming Tong, Prachi Sinha, S. Pande, T. Krishna, J. Romberg, Madhavan Swaminathan, S. Mukhopadhyay
{"title":"A High Performance Computing Architecture for Real-Time Digital Emulation of RF Interactions","authors":"Mandovi Mukherjee, N. M. Rahman, Coleman DeLude, J. Driscoll, Uday Kamal, J. Woo, Jamin Seo, Sudarshan Sharma, Xiangyu Mao, Payman Behnam, Sharjeel Khan, D. Kim, Jianming Tong, Prachi Sinha, S. Pande, T. Krishna, J. Romberg, Madhavan Swaminathan, S. Mukhopadhyay","doi":"10.1109/RadarConf2351548.2023.10149577","DOIUrl":null,"url":null,"abstract":"A high performance architecture for emulating realtime radio frequency systems is presented. The architecture is developed based on a novel compute model and uses nearmemory techniques coupled with highly distributed autonomous control to simultaneously optimize throughput and minimize latency. A cycle level C++ based simulator is used to validate the proposed architecture with simulation of complex RF scenarios.","PeriodicalId":168311,"journal":{"name":"2023 IEEE Radar Conference (RadarConf23)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE Radar Conference (RadarConf23)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RadarConf2351548.2023.10149577","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A high performance architecture for emulating realtime radio frequency systems is presented. The architecture is developed based on a novel compute model and uses nearmemory techniques coupled with highly distributed autonomous control to simultaneously optimize throughput and minimize latency. A cycle level C++ based simulator is used to validate the proposed architecture with simulation of complex RF scenarios.