Design of VLSI sorting accelerator architecture

Abstract

In this paper, the design of VLSI sorter architecture for the acceleration of data sorting operation is addressed. In order to support the sorting of the variable length sequences, the sorter architecture discussed in this paper is based on a central memory module equipped with some fundamental compare-and-swap (C&S) functional units. Three memory-based sorter designs have been addressed. In addition to the basic single-serial C&S architecture, two parallel approaches have been presented. The first approach based on the direct use of parallel C&S units can lead to the speedup of the sorting process nearly proportional to the number of parallel units being used. However, the second approach based on the multi-step cascaded C&S units can further reduce the number of memory data accesses significantly. The dissipation power due to the memory operation can then be reduced such that this approach will be suitable for low-power applications.