Practical implications of chip-level statistical electromigration

Abstract

The accurate setting of electromigration (EM) design guidelines early is necessary to achieve chip-level fail goals. The issue is even more critical with the recognition of the percentage fail as a stochastic issue based on the individual EM elements. The challenge is the degree to fix those elements prior to the knowledge of chip-level fail rate. This paper will demonstrate a test case and approaches to early design guidelines which have shown success at meeting chip-level EM fail goals.