H. Kume, M. Kato, T. Adachi, T. Tanaka, T. Sasaki, T. Okazaki, N. Miyamoto, S. Saeki, Y. Ohji, M. Ushiyama, J. Yugami, T. Morimoto, T. Nishida
{"title":"A 1.28 mu m/sup 2/ contactless memory cell technology for a 3 V-only 64 Mbit EEPROM","authors":"H. Kume, M. Kato, T. Adachi, T. Tanaka, T. Sasaki, T. Okazaki, N. Miyamoto, S. Saeki, Y. Ohji, M. Ushiyama, J. Yugami, T. Morimoto, T. Nishida","doi":"10.1109/IEDM.1992.307524","DOIUrl":null,"url":null,"abstract":"This paper describes a novel contactless memory cell technology for a 3V-only 64Mbit EEPROM with NOR structure. A new program/erase scheme using a Fowler-Nordheim tunneling mechanism is developed, resulting in a single 3V power supply operation. Scatter in \"low-level\" threshold voltage in a memory array, which seriously affects a read operation margin at a reduced V/sub c/c in the NOR structure, is also improved with this scheme. Based on a 0.4 mu m CMOS process, a small cell area of 1.28 mu m/sup 2/ is successfully realized by the contactless memory cell technology, demonstrating the 64Mbit integration capability.<<ETX>>","PeriodicalId":287098,"journal":{"name":"1992 International Technical Digest on Electron Devices Meeting","volume":"215 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 International Technical Digest on Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1992.307524","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper describes a novel contactless memory cell technology for a 3V-only 64Mbit EEPROM with NOR structure. A new program/erase scheme using a Fowler-Nordheim tunneling mechanism is developed, resulting in a single 3V power supply operation. Scatter in "low-level" threshold voltage in a memory array, which seriously affects a read operation margin at a reduced V/sub c/c in the NOR structure, is also improved with this scheme. Based on a 0.4 mu m CMOS process, a small cell area of 1.28 mu m/sup 2/ is successfully realized by the contactless memory cell technology, demonstrating the 64Mbit integration capability.<>
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