Dielectric breakdown in high-K metal gate: Measurement, device level model and application to circuit

Abstract

Gate oxide breakdown is an important reliability issue. This mechanism is widely investigated at device level but the development of a compact model and the assessment at circuit level is much more complex to handle. We first characterize soft and hard breakdown with highlighting the different electrical signatures and sign change of the ratio source drain current. Then a transistor-level model of breakdown is presented. The model is calibrated for a large range of breakdown severity. Finally the model is used at circuit level. The impact of breakdown on both static current and frequency of ring oscillator is discussed.