A 48dB-SFDR, 43dB-SNDR, 50GS/s 9-bit 2x-interleaved Nyquist DAC in Intel 16

Abstract

With the ever-increasing demand for higher throughput in communication systems, data converters require higher conversion rates at moderate resolutions (> 7b) while remaining power efficient. This work presents a 9b, 50GS/s current-steering DAC that achieves a worst case 48.2dBc SFDR in the Nyquist band. A dynamically boosted fast-switching current-cell, 16:1 serializers and AC-coupled coil-less CMOS clock buffers enable a sub-DAC rate of 25GS/s that reduce the interleaving factor to only two. This greatly simplifies calibration and limits the timing-critical areas of the system to the final 2:1 analog multiplexer (MUX). The topology of the current-cell also enables reduced supply voltage for the digital blocks, which leads to a significant reduction in power consumption.