Power-yield optimization in MPSoC task scheduling under process variation

Abstract

Delay and leakage power uncertainty caused by process variation has become a challenging problem in deep sub-micron technologies. In recent years, the designers have developed methods to tackle this problem in many design levels such as high level synthesis and system level synthesis. This paper addresses the problem of variation-aware task scheduling and binding for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis. We use genetic algorithm to find the best schedule that maximizes power-yield under performance-yield constraint. Experimental results on a wide range of real world and random benchmarks show that our proposed algorithm achieves 47% power-yield improvement on average over deterministic worst-case-based scheduling.