Analysis of Subthreshold Finfet Circuits for Ultra-Low Power Design

2006 IEEE International SOC Conference Pub Date : 2006-09-01 DOI:10.1109/SOCC.2006.283853

Xiaoxia Wu, Feng Wang, Yuan Xie

引用次数: 30

Abstract

In this paper, we first explore sub-threshold Fin-FET circuits design space, finding their optimal power supply point for minimum energy consumption. We then study soft error vulnerability in sub-threshold region. Our experiments indicate that the energy consumption in sub-threshold region can achieve 4 orders of magnitude energy saving. Compared to bulk CMOS technology, FinFET circuits have lower functional power supply and lower optimal energy consumption in subthreshold region. In addition, FinFET has better soft error immunity in sub-threshold region.

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超低功耗亚阈值场效应电路分析

在本文中，我们首先探索亚阈值Fin-FET电路的设计空间，寻找其最小能耗的最佳供电点。然后研究了亚阈值区域的软错误漏洞。实验表明，在阈值区域的能耗可以达到4个数量级的节能。与本体CMOS技术相比，FinFET电路具有更低的功能功率和更低的亚阈值区域最优能耗。此外，FinFET在亚阈值区域具有较好的软误差抗扰性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2006 IEEE International SOC Conference

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