Yanjun Zhang, Hu He, Zhixiong Zhou, Xu Yang, Yihe Sun
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引用次数: 3
Abstract
This paper describes a scaleable DSP architecture for ASIP design and a retargetable compiler based on ORC. By configuring this architecture, designers can easily get the ASIP for one set of applications. A DSP named THUASDSP2004 is developed manually based on this architecture and the compiler can give a satisfied result.
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