Leakage Power Reduction Techniques applied to 90-nm SoC Application Processor

Abstract

At the 90-nm, leakage currents bring standby power to an unacceptable level and circuit level techniques become mandatory. However applying these techniques must be robust and practical. In this paper we focus not only on leakage reduction solutions but also on their deployment as a worldwide infrastructure as the added-value resides not only in the techniques themselves but also in the way they are implemented to build an efficient, re-usable, robust, low cost and portable platform. Techniques have been silicon proven on the 90-nm TI CMOS technology and is commonly used to design SoC with complexities over 100 million transistors