{"title":"Design of a Novel FET Frequency Doubler Using a Harmonic Balance Algorithm","authors":"R. Gilmore","doi":"10.1109/MWSYM.1986.1132253","DOIUrl":null,"url":null,"abstract":"The design of a wideband FET frequency doubler operating with a 4-8 GHz input bandwidth is described. The doubler and bandreject amplifier combination achieve an average conversion loss of 3.5 dB across the 8-16 GHz output band. The design method uses the harmonic balance algorithm implemented on an IBM PC-AT personal computer.","PeriodicalId":109161,"journal":{"name":"1986 IEEE MTT-S International Microwave Symposium Digest","volume":"105 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1986-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE MTT-S International Microwave Symposium Digest","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSYM.1986.1132253","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
The design of a wideband FET frequency doubler operating with a 4-8 GHz input bandwidth is described. The doubler and bandreject amplifier combination achieve an average conversion loss of 3.5 dB across the 8-16 GHz output band. The design method uses the harmonic balance algorithm implemented on an IBM PC-AT personal computer.
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