{"title":"Performance evaluation of a DVD processor using transaction level models","authors":"S. Sudharsanan","doi":"10.1109/ISCE.2004.1375972","DOIUrl":null,"url":null,"abstract":"Modern dav DVD processors are classic e.ram& of system-on-chip (SoC) devigns that grew in an incremental fashion over a long period of development. Performance evolnation of s7rch systems consisting of mnltiple heterogeneous processors at the architectural level is a/airl,v complu and time-consuming efort. The traditional approacli qfwing cycle accurate simulotors is slow in sim~ilution speed and is d;ffirzilt in terms ofintegrating tlie SoC model. Al.so, in mony insiunces, siich models are not necessau?, since certain architectriral .fC;utzires snch as the processor interconnection and ronting nehvorks or memou?, system inierfbces are the ones to he determined in ear& design stage.x In this paper. u’e look at performance evaluation of such an SoC for DVD processing hv means of transaction level models zising Sy.7-","PeriodicalId":169376,"journal":{"name":"IEEE International Symposium on Consumer Electronics, 2004","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Consumer Electronics, 2004","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCE.2004.1375972","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Modern dav DVD processors are classic e.ram& of system-on-chip (SoC) devigns that grew in an incremental fashion over a long period of development. Performance evolnation of s7rch systems consisting of mnltiple heterogeneous processors at the architectural level is a/airl,v complu and time-consuming efort. The traditional approacli qfwing cycle accurate simulotors is slow in sim~ilution speed and is d;ffirzilt in terms ofintegrating tlie SoC model. Al.so, in mony insiunces, siich models are not necessau?, since certain architectriral .fC;utzires snch as the processor interconnection and ronting nehvorks or memou?, system inierfbces are the ones to he determined in ear& design stage.x In this paper. u’e look at performance evaluation of such an SoC for DVD processing hv means of transaction level models zising Sy.7-
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