{"title":"A Ka-band low power and high-efficiency differential power amplifier in 0.25-μm BiCMOS","authors":"M. Balducci, H. Schumacher, S. Chartier","doi":"10.1109/INMMIC.2017.7927315","DOIUrl":null,"url":null,"abstract":"A Ka-band power amplifier (PA) in a differential cascode topology with active biasing is designed, implemented in a 0.25 μm SiGe BiCMOS technology, and characterized. The design presents low power consumption and high Power Added Efficiency (PAE). This PA presents an output power of 12.3 dBm at P1dB with 16.5% Power Added Efficiency (PAE). The PAE peak is 17.5 % and it is centered nearby the P1dB. The consumed power is lower than 100 mW at the P1dB with a supply voltage of 3.3 V. Including the measurements pads the IC occupies an area of 870 μm × 780 μm.","PeriodicalId":322300,"journal":{"name":"2017 Integrated Nonlinear Microwave and Millimetre-wave Circuits Workshop (INMMiC)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Integrated Nonlinear Microwave and Millimetre-wave Circuits Workshop (INMMiC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INMMIC.2017.7927315","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A Ka-band power amplifier (PA) in a differential cascode topology with active biasing is designed, implemented in a 0.25 μm SiGe BiCMOS technology, and characterized. The design presents low power consumption and high Power Added Efficiency (PAE). This PA presents an output power of 12.3 dBm at P1dB with 16.5% Power Added Efficiency (PAE). The PAE peak is 17.5 % and it is centered nearby the P1dB. The consumed power is lower than 100 mW at the P1dB with a supply voltage of 3.3 V. Including the measurements pads the IC occupies an area of 870 μm × 780 μm.
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