Design and FPGA implementation of JPEG-LS image decompression

Abstract

As the resolution of images processed in real-time continues to increase, it is necessary to compress the transmitted image data, and then transmit it to the terminal to decompress and restore the image. JPEG-LS is an algorithm that supports lossless and near-lossless compression. However, the decompression of JPEG-LS images is mostly implemented in a software environment. When decompressing multiple high-resolution images, the problems of decoding speed and resource consumption are more prominent. Therefore, the implementation of the JPEG-LS image decompression algorithm on FPGA is proposed in this paper, which divides the image into blocks and adopts a parallel processing structure. After the experiment on the hardware decoder, for the 1024*2048 test image, the designed hardware decoder can improve the original software decoding time by approximately 55%.