K. Kitamura, K. Nakai, H. Matsui, T. Nagao, Y. Norimitsu
{"title":"Novel exposure system for FOWLP and MCM photolithopraphy process","authors":"K. Kitamura, K. Nakai, H. Matsui, T. Nagao, Y. Norimitsu","doi":"10.1109/ICSJ.2014.7009621","DOIUrl":null,"url":null,"abstract":"Fan-out process is one of the major technologies within WLP(Wafer Level Package), where silicon chips are buried into the mold substrate. (Fan-Out WLP)(Fig.1, 2)[1] We have developed the exposure system applying advantage of direct imaging technology with using no-mask or reticle. The system has the capability of compensating displacement of the chips on the reconfigured substrate. We have been successful that the system was able to do alignment exposure with accuracy of equal or less than 2um at |Ave.| + 3 σ.","PeriodicalId":362502,"journal":{"name":"IEEE CPMT Symposium Japan 2014","volume":"92 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE CPMT Symposium Japan 2014","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSJ.2014.7009621","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Fan-out process is one of the major technologies within WLP(Wafer Level Package), where silicon chips are buried into the mold substrate. (Fan-Out WLP)(Fig.1, 2)[1] We have developed the exposure system applying advantage of direct imaging technology with using no-mask or reticle. The system has the capability of compensating displacement of the chips on the reconfigured substrate. We have been successful that the system was able to do alignment exposure with accuracy of equal or less than 2um at |Ave.| + 3 σ.