Delay and transient response modelling of on-chip RLCG interconnect using two-port network functions

Abstract

This paper presents a novel and accurate analytical approach for the efficient computation of the transient response and 50% delay of on-chip RLCG interconnect lines with a capacitive load. The proposed model is based on the two port representation of the transmission line. The simulation results are obtained by using the proposed model and found to be at good agreement with that of the SPICE simulation results. The results obtained justify the accuracy and the validity of the proposed transient response and the delay model for a wide range of load impedance values. The minimum error has been calculated to be 2.65% while the maximum error is found to be 8.33%.