Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment

Abstract

As IC technology scales down, signal integrity issues such as power supply noise and clock skews are becoming one of the major concerns of gigahertz system-on-chip (SoC) design. Considering that one of the most important mechanisms to degrade signal integrity is electromagnetic interference (EMI), this paper analyzes the effectiveness of a clock duty-cycle (CDC) modulation technique to enhance SoC signal integrity with respect to power/ground voltage transients induced by EMI. The technique is based on a clock stretching logic (CSL) block, which monitors abnormal power grid activity and increases CDC accordingly. Practical experiments based on the implementation of a 32-bit soft-core pipeline processor in an FPGA IC were performed and illustrate the circuit robustness enhancement to power line fluctuations while maintaining at-speed clock rate. These experiments were conducted according to the IEC 62.132-2. Normative for measurement of radiated electromagnetic immunity (TEM-cell method).