HeroeS: Virtual platform driven integration of heterogeneous software components for multi-core real-time architectures

Abstract

This article presents the HeroeS virtual platform driven methodology for embedded multi-core and real-time SW design. The methodology's focus is on early integration, testing and performance estimation of heterogeneous SW stacks, i.e., SW components and layers at mixed abstraction levels and/or targeting different instruction sets. We take into account current system-level methodologies such as Transaction Level Modeling (TLM) and Real-Time Operating System (RTOS) modeling. For this, a SystemC virtual platform framework is presented combining state of the art simulation techniques according to the proposed methodology. This includes host-compiled target SW abstraction, abstract RTOS and Hardware Abstraction Layer (HAL) models in SystemC, extended QEMU user and system mode emulation and TLM 2.0 bus models. Efficient but yet accurate performance estimates can be provided through static and dynamic annotation. We apply binary mutation testing, i.e, a test assessment and improvement approach for instruction level SW testing. Our approach was investigated by prototypical integration into a commercial AUTOSAR environment. Experimental results were obtained by an automotive case study: a fault-tolerant fuel injection control system, which is part of an in-car network.