Datapath-oriented FPGA mapping and placement for configurable computing

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) Pub Date : 1997-04-16 DOI:10.1109/FPGA.1997.624624

T. Callahan, J. Wawrzynek

引用次数: 2

Abstract

Widespread acceptance of FPGA-based reconfigurable coprocessors will be expedited if compilation time for FPGA configurations can be reduced to be comparable to software compilation. This research achieves this goal, generating complete datapath layouts in fractions of a second rather than hours. Our algorithm, adapted from instruction selection in compilers, packs multiple operations into single rows of CLBs when possible, while preserving a regular bit-slice layout. Furthermore, placement and thus routing delays are considered simultaneously with packing, so that the total delay, not just the CLB delay, is optimized.

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面向数据路径的FPGA映射和可配置计算的放置

如果FPGA配置的编译时间可以减少到与软件编译相当，那么基于FPGA的可重构协处理器的广泛接受将会加快。这项研究实现了这一目标，在几分之一秒而不是几个小时内生成完整的数据路径布局。我们的算法改编自编译器中的指令选择，尽可能将多个操作打包到单行clb中，同时保留常规的位片布局。此外，放置和路由延迟与分组同时考虑，以便优化总延迟，而不仅仅是CLB延迟。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)

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