W. Syafei, R. Yohena, H. Shimajiri, T. Yoshida, M. Kurosaki, Y. Nagao, B. Sai, H. Ochi
{"title":"Performance Evaluation and ASIC Design of LDPC Decoder for IEEE802.11n","authors":"W. Syafei, R. Yohena, H. Shimajiri, T. Yoshida, M. Kurosaki, Y. Nagao, B. Sai, H. Ochi","doi":"10.1109/CCNC.2009.4784735","DOIUrl":null,"url":null,"abstract":"This paper presents our investigation on performance enhancement due to the implementation of low density parity check (LDPC) codes on IEEE 802.11n system and its Application Specific Integrated Circuit design. Simulation result shows that in higher coding rate, LDPC codes gives 6 dB better performance compared to binary convolutional codes. Logic synthesis is succesfully done on 0.13 µm CMOS technology with low-power standard cell library.","PeriodicalId":181188,"journal":{"name":"2009 6th IEEE Consumer Communications and Networking Conference","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 6th IEEE Consumer Communications and Networking Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CCNC.2009.4784735","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents our investigation on performance enhancement due to the implementation of low density parity check (LDPC) codes on IEEE 802.11n system and its Application Specific Integrated Circuit design. Simulation result shows that in higher coding rate, LDPC codes gives 6 dB better performance compared to binary convolutional codes. Logic synthesis is succesfully done on 0.13 µm CMOS technology with low-power standard cell library.