A cross-layer approach to online adaptive reliability prediction of transient faults

Abstract

As the semiconductor industry migrates into the nanometer regime, processors become increasingly susceptible to transient faults. Such faults usually stem either from soft errors due to particle strikes or timing violations due to Process, Voltage, Temperature, and Aging (PVTA) variations. These faults can propagate from circuit-level to application-level and alter the correct execution output of the application. For generations, designers build high-level resiliency such that the details of the underlying circuit are an abstraction that could be neglected. This paper argues that in contrast to the prior work, which only take into account Architectural Vulnerability Factor (AVF) as a measure to guide fault tolerant techniques, the vulnerability of each abstraction layer of design stack from circuit going up to instruction and application layers should be considered. This paper presents a novel online cross-layer reliability prediction technique based on learning algorithms which can anticipate the susceptibility of the processor considering both lower-level and higher-level details in an adaptive fashion. According to the results, the proposed technique can predict the future reliability with 6% error on average across SPEC2000 benchmarks. Our technique by forecasting the reliability emergencies can assist proactive fault tolerant techniques to maintain the reliability constraints more efficiently in comparison to reactive strategies.