Three Dimensional Design and Implementation of Doped-Pocket Substrate in N-MOSFET

2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCA) Pub Date : 2018-07-01 DOI:10.1109/ICSCAN.2018.8541208

P. Saha

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引用次数: 2

Abstract

A moderatley doped pocket is implemented in the substrate of an N-MOSFET. Three dimensional simulation modelling of the device has been carried out such that the W/L ratio can be varied. Input output characteristics of the device is obtianed from the simulation which follows the characteristics of the conventional MOSFET. In order to perfrom analysis and comparison the device designed with different channel length ranging from 20nm to 40nm, width of the device is varied from 22nm to 2um. Device characteristics are also obtained for the device with different dimension by keeping the W/L ratio constant and variable. It has been observed that for constant W/L ratio the drain current remains almost constant and for different W/L ratio the drain current changes with the same fraction as that of W/L ratio. On Being comparing the results with the conventional one this modified MOSFET gives better results in terms of both input and output characteristics. Leakage current analysis signifies that modified drain characteristics has a narrower slope.

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N-MOSFET掺杂口袋基板的三维设计与实现

在N-MOSFET的衬底中实现了适度掺杂的口袋。该装置的三维仿真建模已经进行，使W/L比可以变化。通过仿真得到了器件的输入输出特性，该特性遵循了传统的MOSFET的特性。为了进行分析和比较，设计了不同通道长度从20nm到40nm的器件，器件宽度从22nm到2um不等。通过保持W/L比恒定和可变，得到了不同尺寸器件的器件特性。当W/L比恒定时，漏极电流几乎保持不变，当W/L比不同时，漏极电流的变化幅度与W/L比相同。通过与传统的MOSFET进行比较，改进后的MOSFET在输入和输出特性方面都得到了更好的结果。泄漏电流分析表明，改进后的漏极特性斜率较窄。

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2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCA)

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