Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS

Abstract

Fully-depleted SOI/CMOS transistors were fabricated using titanium-nitride (TiN) gates with near midgap work-function in order to optimize the p- and n-channel threshold voltages for operation at low supply voltage. To simplify the process as well as to minimize the strain, a novel gate structure was used in which a thick polysilicon (300 nm) was stacked on a thin TiN layer (<50 nm). Excellent symmetrical subthreshold characteristics were obtained with relatively low values of threshold voltage and low off-state leakages. The subthreshold swing, transconductance, and saturation drain current were comparable with those for conventional n/sup +//p/sup +/ polysilicon gates. In addition, hot-carrier stress results indicate no significant differences from the poly-gate cases.<>