Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs

IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI:10.1109/CICC.2006.320991

V. Iyengar, Mark Johnson, Theo Anemikos, Gary Grise, Mark Taylor, Raymond Farmer, F. Woytowich, Bob Bassett

引用次数: 2

Abstract

Performance verification is critical to high-performance ASICs manufacturing. Performance verification ensures that only those chips whose performance is higher than an advertised threshold are shipped to demanding customers. This provides a means to weed out nominal performance ASICs, and also ship ASICs at difference grades. At-speed structural test can provide performance verification capability at very low cost. In this paper, we present a scalable and flexible structural test method for performance verification of ASICs. The proposed method requires no tight restrictions on the circuit design. Moreover, low-cost testers are used, thus sharply reducing test cost

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高性能asic的高速结构测试与性能验证设计

性能验证是高性能asic制造的关键。性能验证确保只有那些性能高于广告阈值的芯片才会被运送给要求苛刻的客户。这提供了一种淘汰标称性能asic的方法，也提供了不同等级的asic。高速结构试验可以以非常低的成本提供性能验证能力。本文提出了一种可扩展和灵活的结构测试方法，用于asic的性能验证。该方法对电路设计没有严格的限制。此外，使用了低成本的测试仪，从而大大降低了测试成本

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE Custom Integrated Circuits Conference 2006

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