DESIGN OF A REVERSIBLE FUSED 32-POINT RADIX -2 FLOATING POINT FFT UNIT USING 3:2 COMPRESSOR

Abstract

This paper aims on the design of a reversible fused 32Point Radix-2 single precision floating point FFT unit using 3:2 compressor. The work focuses on the realization of three reversible fused floating point units: reversible floating point add-sub unit, reversible floating point multiply-add unit and reversible floating point multiply-subtract unit. The proposed work requires the design of a reversible single precision floating point adder, a reversible single precision floating point subtractor and a reversible single precision floating point multiplier. A reversible single precision floating point adder and subtractor is designed with less quantum cost, less number of reversible gates and less constant inputs. A reversible single precision floating point multiplier is implemented using 3:2 compressor as the 24x24 bit multiplier based on 3:2 compressor is highly efficient when compared with the design using 4:3 compressors. A reversible fused 32-Point Radix-2 floating point FFT Unit using 3:2 compressor consumes less number of resources, operates at a slightly greater speed and dissipates less power when compared with the reversible discrete 32-Point Radix-2 floating point FFT Unit. The proposed Fused 32-Point Radix-2 floating point FFT unit using 3:2 compressor dissipates 2.074W while the same design as a discrete implementation dissipates 2.176W.