A Low Power SRAM Architecture Based on Segmented Virtual Grounding

Abstract

A novel architecture for the reduction of both dynamic and static power consumption of static random access memories (SRAM) is presented. The scheme is based on the segmented virtual grounding (SVGND) of the SRAM cells. Substantial leakage reduction is achieved by increasing the threshold voltage of the cell transistors through body effect. The write and read energy consumptions are reduced significantly by decreasing the bitline voltage swing and the number of bitlines affected in each transaction. Unlike recently reported low-power schemes, SVGND allows multiple words to be placed in each row while keeping the dynamic power low. This feature is achieved by introducing an additional operation mode to the SRAM cells. The architecture is implemented in a 130nm CMOS technology. Using this scheme, the read and write array energy consumption can be saved by 44% and 84% respectively. Measurement results portraits 15 times leakage reduction compared to the conventional scheme