CMOS LNA design at 30 GHz — A case study

Abstract

This paper presents a case study of LNA design at 30 GHz. Two single-stage LNA topologies are implemented, namely a magnetic feedback LNA and a cascode LNA. The simulation results reveal that a single-stage LNA can deliver adequate power gain along with low noise figure and high linearity even at mm-wave frequencies. The cascode LNA topology, using SNIM is analyzed and described in detail. The post layout simulations give a forward gain (S21) of 5.9 dB, a reverse isolation (-S12) of 18.1 dB, an input reflection (S11) of -11.8 dB and an output reflection (S22) of -11.4 dB. The NF of the circuit is 3.9 dB while the corresponding IIP3 is 4.9 dBm. The power consumption is 7.2 mW and the circuit occupies 0.37 mm2 including the pads. The design is implemented in TSMC's LP 90 nm CMOS process.