Design of a 1.8V 8-bit 500MSPS folding-interpolation CMOS A/D converter with a folder averaging technique

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18mu m 1-poly 5-metal CMOS technology. The active chip area is 0.79 mm2 and it consumes about 200 mW at 1.8 V power supply. The DNL and INL are within plusmn0.6/plusmn0.6LSB, respectively. The measured result of SNDR is 47.05dB.