Temperature-Aware Floorplanning of Microarchitecture Blocks with IPC-Power Dependence Modeling and Transient Analysis

Vidyasagar Nookala, D. Lilja, S. Sapatnekar
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引用次数: 30

Abstract

Operating temperatures have become an important concern in high performance microprocessors. Floorplanning or block-level placement offers excellent potential for thermal optimization through better heat spreading between the blocks, but these optimizations can also impact the throughput of a microarchitecture, measured in terms of the number of instructions per cycle (IPC). In nanometer technologies, global buses can have multicycle delays that depend on the positions of the blocks, and it is important for a floorplanner to be microarchitecturally-aware to be sure that thermal and IPC considerations are appropriately balanced. This paper proposes a methodology for thermally-aware microarchitecture floorplanning. The approach models the interactions between the IPC and the temperature distribution, and incorporates both factors in the floorplanning cost function. Our approach uses transient modeling and optimizes both the peak and the average temperatures, and employs a design of experiments (DOE) based strategy, which effectively captures the huge exponential search space with a small number of cycle-accurate simulations. A comparison with a technique based on previous work indicates that the proposed approach results in good reductions both in the average and the peak temperatures for a range of SPEC benchmarks
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基于ipc -功率依赖建模和瞬态分析的微架构块的温度感知布局
工作温度已经成为高性能微处理器的一个重要问题。地板规划或块级布局通过更好地在块之间传播热量,为热优化提供了极好的潜力,但这些优化也会影响微架构的吞吐量,以每周期指令数(IPC)来衡量。在纳米技术中,全局总线可能有多周期延迟,这取决于块的位置,对于地板规划人员来说,了解微架构以确保适当平衡散热和IPC考虑是很重要的。本文提出了一种热敏感微建筑平面规划方法。该方法模拟了IPC和温度分布之间的相互作用,并将这两个因素纳入了地板规划成本函数中。该方法采用瞬态建模,对峰值和平均温度进行优化,并采用基于实验设计(DOE)的策略,通过少量周期精确的模拟,有效地捕获了巨大的指数搜索空间。与基于先前工作的技术的比较表明,所提出的方法可以很好地降低SPEC基准范围内的平均温度和峰值温度
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