A new approach to simultaneous buffer insertion and wire sizing

Lei He, A. Kahng, K. Tam, Jinjun Xiong
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引用次数: 36

Abstract

We present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore some special properties of our problem and derive on optimal and very efficient algorithm to solve the resulting program. Given m buffers and a set of n discrete choices of wire width, the running time of our algorithm is O(mn/sup 2/) and is independent of the wire length in practice. For example, an instance of 100 buffers and 100 choices of wire width can be solved in 3 seconds. Besides, our formulation is so versatile that it is easy to consider other objectives like wire area or power dissipation, or to add constraints to the solution. Also, wire capacitance lookup tables, or very general wire capacitance models which can capture area capacitance, fringing capacitance, coupling capacitance, etc. can be used.
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一种同时进行缓冲区插入和导线大小调整的新方法
我们提出了一种全新的方法,通过同时插入缓冲器和导线尺寸来解决导线延迟最小化问题。我们证明了这个问题可以被表述为一个凸二次规划,它可以在多项式时间内求解。然而,我们探索了这个问题的一些特殊性质,并推导出一个最优的、非常有效的算法来解决所得到的程序。给定m个缓冲区和一组n个离散的导线宽度选择,我们的算法的运行时间为O(mn/sup 2/),并且在实践中与导线长度无关。例如,一个有100个缓冲器和100个导线宽度选择的实例可以在3秒内解决。此外,我们的公式是如此通用,很容易考虑其他目标,如线面积或功耗,或添加约束的解决方案。此外,还可以使用线电容查找表或非常通用的线电容模型,这些模型可以捕获面积电容、边缘电容、耦合电容等。
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