Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643360
M. Hsiao, E. Rudnick, J. Patel
Previous work has shown that maximum switching density at a given node is extremely sensitive to a slight change in the delay at that node. However, when estimating the peak power for the entire circuit, the powers estimated must not be as sensitive to a slight variation or inaccuracy in the assumed gate delays because computing the exact gate delays for every gate in the circuit during simulation is expensive. Thus, we would like to use the simplest delay model possible to reduce the execution time for estimating power, while making sure that it provides an accurate estimate, i.e., that the peak powers estimated will not vary due to a variation in the gate delays. Results for four delay models are reported for the ISCAS85 combinational benchmark circuits, ISCAS89 sequential benchmark circuits, and several synthesized circuits.
{"title":"Effects of delay models on peak power estimation of VLSI sequential circuits","authors":"M. Hsiao, E. Rudnick, J. Patel","doi":"10.1109/ICCAD.1997.643360","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643360","url":null,"abstract":"Previous work has shown that maximum switching density at a given node is extremely sensitive to a slight change in the delay at that node. However, when estimating the peak power for the entire circuit, the powers estimated must not be as sensitive to a slight variation or inaccuracy in the assumed gate delays because computing the exact gate delays for every gate in the circuit during simulation is expensive. Thus, we would like to use the simplest delay model possible to reduce the execution time for estimating power, while making sure that it provides an accurate estimate, i.e., that the peak powers estimated will not vary due to a variation in the gate delays. Results for four delay models are reported for the ISCAS85 combinational benchmark circuits, ISCAS89 sequential benchmark circuits, and several synthesized circuits.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128599185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643588
A. Kalavade, 07733. subra
We are interested in optimizing the design of multi-function embedded systems that run a pre-specified set of applications, such as multi-standard audio/video codecs and multi-system phones. Such systems usually have stringent performance constraints and tend to have mixed hardware-software implementations. The current stare of the art in the hardware/software codesign of such systems is to design for each application separately. This often leads to application-specific sub-optimal decisions and inconsistent mappings of common nodes in different applications. We use these as the guiding principles to formulate, as a codesign problem, the design and synthesis of an efficient hardware-software implementation for a multi-function embedded system. Our solution methodology is to first identify nodes that represent similar functionality across different applications. Such "common" nodes are characterized by several metrics. These metrics are quantified and used by a hardware/software partitioning tool to map common nodes to the same resource as far as possible. We demonstrate how this is achieved by modifying a traditional partitioning algorithm (GCLP) used to partition single applications. The overall result of the system-level partitioning process is (1) a hardware or software mapping and (2) a schedule for execution for each node within the application set. On an example set consisting of three video applications, we show that the solution obtained by the use of our method is 38% smaller than that obtained when each application is considered independently.
{"title":"Hardware/software partitioning for multi-function systems","authors":"A. Kalavade, 07733. subra","doi":"10.1109/ICCAD.1997.643588","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643588","url":null,"abstract":"We are interested in optimizing the design of multi-function embedded systems that run a pre-specified set of applications, such as multi-standard audio/video codecs and multi-system phones. Such systems usually have stringent performance constraints and tend to have mixed hardware-software implementations. The current stare of the art in the hardware/software codesign of such systems is to design for each application separately. This often leads to application-specific sub-optimal decisions and inconsistent mappings of common nodes in different applications. We use these as the guiding principles to formulate, as a codesign problem, the design and synthesis of an efficient hardware-software implementation for a multi-function embedded system. Our solution methodology is to first identify nodes that represent similar functionality across different applications. Such \"common\" nodes are characterized by several metrics. These metrics are quantified and used by a hardware/software partitioning tool to map common nodes to the same resource as far as possible. We demonstrate how this is achieved by modifying a traditional partitioning algorithm (GCLP) used to partition single applications. The overall result of the system-level partitioning process is (1) a hardware or software mapping and (2) a schedule for execution for each node within the application set. On an example set consisting of three video applications, we show that the solution obtained by the use of our method is 38% smaller than that obtained when each application is considered independently.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126908302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643533
Tuyen V. Nguyen, A. Devgan
This paper presents a general method for incorporating state transformation in event driven explicit simulation. One inherent assumption in this type of simulation algorithm is the state independence, which allows the algorithm to process the states independently in an event driven manner at the transistor level. Numerical problems arise when an inappropriate state representation of the circuit, in which the states are not truly independent, is chosen. In principle, any similarity transformation of the state equation can be employed to transform the circuit into a more convenient state space for numerical solution. This paper develops a systematic scheme to derive an appropriate state transformation, and to incorporate the state transformulation in such a way to maintain the efficiency of event driven explicit simulation algorithms.
{"title":"State transformation in event driven explicit simulation","authors":"Tuyen V. Nguyen, A. Devgan","doi":"10.1109/ICCAD.1997.643533","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643533","url":null,"abstract":"This paper presents a general method for incorporating state transformation in event driven explicit simulation. One inherent assumption in this type of simulation algorithm is the state independence, which allows the algorithm to process the states independently in an event driven manner at the transistor level. Numerical problems arise when an inappropriate state representation of the circuit, in which the states are not truly independent, is chosen. In principle, any similarity transformation of the state equation can be employed to transform the circuit into a more convenient state space for numerical solution. This paper develops a systematic scheme to derive an appropriate state transformation, and to incorporate the state transformulation in such a way to maintain the efficiency of event driven explicit simulation algorithms.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123683681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643615
Jeffrey Z. Su, W. Dai
The paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification without further modifications. However, to improve manufacturability, the authors introduce a concept called even wire distribution, a key element of the SURF physical design tool. To alleviate congestion, they first move vias and wires towards less dense areas in a manner which preserves the existing wiring paths. Depending on the locally available area, they then increase wire spacing to reduce defect sensitivity, without changing the area of the design. Carafe, an inductive fault analysis tool is used to evaluate the new layout.
{"title":"Post-route optimization for improved yield using a rubber-band wiring model","authors":"Jeffrey Z. Su, W. Dai","doi":"10.1109/ICCAD.1997.643615","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643615","url":null,"abstract":"The paper presents a unique approach to improve yield given a routed layout. Currently after routing has been completed and compacted, it generally proceeds to verification without further modifications. However, to improve manufacturability, the authors introduce a concept called even wire distribution, a key element of the SURF physical design tool. To alleviate congestion, they first move vias and wires towards less dense areas in a manner which preserves the existing wiring paths. Depending on the locally available area, they then increase wire spacing to reduce defect sensitivity, without changing the area of the design. Carafe, an inductive fault analysis tool is used to evaluate the new layout.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114077289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643403
D. Kirovski, M. Potkonjak
We introduce a novel cut-based debugging paradigm. It coordinates design emulation and simulation and enables fast transition from one to another. Emulation or functional implementation is used for fast application execution; simulation provides complete design observability and controllability. The implementation of the new debugging approach poses several CAD tasks. We formulate the optimization tasks and develop constraint-based heuristics to solve them. Effectiveness of the approach is demonstrated on a set of designs.
{"title":"A quantitative approach to functional debugging","authors":"D. Kirovski, M. Potkonjak","doi":"10.1109/ICCAD.1997.643403","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643403","url":null,"abstract":"We introduce a novel cut-based debugging paradigm. It coordinates design emulation and simulation and enables fast transition from one to another. Emulation or functional implementation is used for fast application execution; simulation provides complete design observability and controllability. The implementation of the new debugging approach poses several CAD tasks. We formulate the optimization tasks and develop constraint-based heuristics to solve them. Effectiveness of the approach is demonstrated on a set of designs.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114616109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643368
I. Elfadel, D. D. Ling
Work in the area of model-order reduction for RLC interconnect networks has focused on building reduced-order models that preserve the circuit-theoretic properties of the network, such as stability, passivity, and synthesizability (Silveira et al., 1996). Passivity is the one circuit-theoretic property that is vital for the successful simulation of a large circuit netlist containing reduced-order models of its interconnect networks. Non-passive reduced-order models may lead to instabilities even if they are themselves stable. We address the problem of guaranteeing the accuracy and passivity of reduced-order models of multiport RLC networks at any finite number of expansion points. The novel passivity-preserving model-order reduction scheme is a block version of the rational Arnoldi algorithm (Ruhe, 1994). The scheme reduces to that of (Odabasioglu et al., 1997) when applied to a single expansion point at zero frequency. Although the treatment of this paper is restricted to expansion points that are on the negative real axis, it is shown that the resulting passive reduced-order model is superior in accuracy to the one that would result from expanding the original model around a single point. Nyquist plots are used to illustrate both the passivity and the accuracy of the reduced order models.
RLC互连网络模型降阶领域的工作主要集中在建立保持网络电路理论特性的降阶模型，如稳定性、无源性和可合成性(Silveira et al.， 1996)。无源性是电路理论的一个重要性质，它对包含其互连网络的降阶模型的大型电路网络表的成功仿真至关重要。非被动降阶模型可能导致不稳定，即使它们本身是稳定的。研究了多端口RLC网络在任意有限个数的扩展点上的降阶模型的准确性和无源性的保证问题。新的无源保持模型阶约简方案是理性Arnoldi算法的块版本(Ruhe, 1994)。当应用于零频率的单个扩展点时，该方案减少到(Odabasioglu et al.， 1997)。虽然本文的处理仅限于负实轴上的展开点，但结果表明，所得的被动降阶模型的精度优于围绕单个点展开原始模型的模型。用奈奎斯特图说明了降阶模型的无源性和精度。
{"title":"A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks","authors":"I. Elfadel, D. D. Ling","doi":"10.1109/ICCAD.1997.643368","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643368","url":null,"abstract":"Work in the area of model-order reduction for RLC interconnect networks has focused on building reduced-order models that preserve the circuit-theoretic properties of the network, such as stability, passivity, and synthesizability (Silveira et al., 1996). Passivity is the one circuit-theoretic property that is vital for the successful simulation of a large circuit netlist containing reduced-order models of its interconnect networks. Non-passive reduced-order models may lead to instabilities even if they are themselves stable. We address the problem of guaranteeing the accuracy and passivity of reduced-order models of multiport RLC networks at any finite number of expansion points. The novel passivity-preserving model-order reduction scheme is a block version of the rational Arnoldi algorithm (Ruhe, 1994). The scheme reduces to that of (Odabasioglu et al., 1997) when applied to a single expansion point at zero frequency. Although the treatment of this paper is restricted to expansion points that are on the negative real axis, it is shown that the resulting passive reduced-order model is superior in accuracy to the one that would result from expanding the original model around a single point. Nyquist plots are used to illustrate both the passivity and the accuracy of the reduced order models.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"50 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124528501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643617
J. Cong, Cheng-Kok Koh
Studies the interconnect layout optimization problem under a higher-order RLC model to optimize not just the delay but also the waveform for RLC circuits with non-monotone signal response. We propose a unified approach that considers topology optimization, wire-sizing optimization and waveform optimization simultaneously. Our algorithm considers a large class of routing topologies, ranging from shortest-path Steiner trees to bounded-radius Steiner trees and Steiner routings. We construct a set of required-arrival-time Steiner (RATS) trees, providing a smooth trade-off among signal delay, waveform and routing area. Using a new incremental moment computation algorithm, we interleave topology construction with moment computation to facilitate accurate delay calculation and evaluation of waveform quality. Experimental results show that our algorithm is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot and routing cost.
{"title":"Interconnect layout optimization under higher-order RLC model","authors":"J. Cong, Cheng-Kok Koh","doi":"10.1109/ICCAD.1997.643617","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643617","url":null,"abstract":"Studies the interconnect layout optimization problem under a higher-order RLC model to optimize not just the delay but also the waveform for RLC circuits with non-monotone signal response. We propose a unified approach that considers topology optimization, wire-sizing optimization and waveform optimization simultaneously. Our algorithm considers a large class of routing topologies, ranging from shortest-path Steiner trees to bounded-radius Steiner trees and Steiner routings. We construct a set of required-arrival-time Steiner (RATS) trees, providing a smooth trade-off among signal delay, waveform and routing area. Using a new incremental moment computation algorithm, we interleave topology construction with moment computation to facilitate accurate delay calculation and evaluation of waveform quality. Experimental results show that our algorithm is able to construct a set of topologies providing a smooth trade-off among signal delay, signal settling time, voltage overshoot and routing cost.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131648608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643371
V. Bertacco, M. Damiani
We present an algorithm for extracting a disjunctive decomposition from the BDD representation of F. The output of the algorithm is a multiple-level netlist exposing the hierarchical decomposition structure of the function. The algorithm has theoretical quadratic complexity in the size of the input BDD. Experimentally, we were able to decompose most synthesis benchmarks in less than one second of CPU time, and to report on the decomposability of several complex ISCAS combinational benchmarks. We found the final netlist to be often close to the output of more complex dedicated optimization tools.
{"title":"The disjunctive decomposition of logic functions","authors":"V. Bertacco, M. Damiani","doi":"10.1109/ICCAD.1997.643371","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643371","url":null,"abstract":"We present an algorithm for extracting a disjunctive decomposition from the BDD representation of F. The output of the algorithm is a multiple-level netlist exposing the hierarchical decomposition structure of the function. The algorithm has theoretical quadratic complexity in the size of the input BDD. Experimentally, we were able to decompose most synthesis benchmarks in less than one second of CPU time, and to report on the decomposability of several complex ISCAS combinational benchmarks. We found the final netlist to be often close to the output of more complex dedicated optimization tools.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"66 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131122103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643612
V. Székely, M. Rencz
To solve the problem of fast thermal and electrostatic simulation of microsystem elements two different field solver tools have been developed at TUB. The /spl mu/S-THERMANAL program is capable for the fast steady state and dynamic simulation of suspended multilayered microsystem structures, while the 2D-SUNRED program is the first version of a general field solver program, based on an original method, successive network reduction. This program offers a very fast and accurate substitute for FEM programs for the solution of the Poisson equation, e.g. solving a 32000 grid problem in about 6 minutes on a 586 PC. Application examples show the usability of the tools.
{"title":"Fast field solver programs for thermal and electrostatic analysis of microsystem elements","authors":"V. Székely, M. Rencz","doi":"10.1109/ICCAD.1997.643612","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643612","url":null,"abstract":"To solve the problem of fast thermal and electrostatic simulation of microsystem elements two different field solver tools have been developed at TUB. The /spl mu/S-THERMANAL program is capable for the fast steady state and dynamic simulation of suspended multilayered microsystem structures, while the 2D-SUNRED program is the first version of a general field solver program, based on an original method, successive network reduction. This program offers a very fast and accurate substitute for FEM programs for the solution of the Poisson equation, e.g. solving a 32000 grid problem in about 6 minutes on a 586 PC. Application examples show the usability of the tools.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133451966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-11-13DOI: 10.1109/ICCAD.1997.643591
Shinji Sato
This paper addresses a placement method for module generation. The conventional partitioning based method can not guarantee the best results in consecutive partitioning. Also, when the size of the cells varies greatly, it can be too strong a constraint for minimum partitioning under "partitioning into two similar size subcircuits". Although the conventional simulated annealing (SA) based method gives a better result, it requires extremely long computation time. This paper proposes an algorithm based on SA method which employs the divide and conquer technique to give better results than partitioning based method and to give a much faster computation time than SA method. We applied this idea to linear placement. It was found that the total wiring length was improved by about 10% compared to that of the spectral method (previously recognized to be the best). The computation time was greatly reduced from the SA method.
{"title":"Simulated quenching: a new placement method for module generation","authors":"Shinji Sato","doi":"10.1109/ICCAD.1997.643591","DOIUrl":"https://doi.org/10.1109/ICCAD.1997.643591","url":null,"abstract":"This paper addresses a placement method for module generation. The conventional partitioning based method can not guarantee the best results in consecutive partitioning. Also, when the size of the cells varies greatly, it can be too strong a constraint for minimum partitioning under \"partitioning into two similar size subcircuits\". Although the conventional simulated annealing (SA) based method gives a better result, it requires extremely long computation time. This paper proposes an algorithm based on SA method which employs the divide and conquer technique to give better results than partitioning based method and to give a much faster computation time than SA method. We applied this idea to linear placement. It was found that the total wiring length was improved by about 10% compared to that of the spectral method (previously recognized to be the best). The computation time was greatly reduced from the SA method.","PeriodicalId":187521,"journal":{"name":"1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)","volume":"243 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132729527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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