{"title":"A Linear Mode CMOS Power Amplifier with Self-Linearizing Bias","authors":"R.D. Singh, Kyung-Wan Yu","doi":"10.1109/ASSCC.2006.357898","DOIUrl":null,"url":null,"abstract":"A biasing scheme that improves the linearity of linear mode power amplifiers (PA) is presented. This technique employs adding feedback to a current mirror bias to enhance the linearity of the amplifier by compensating the nonlinear input capacitance of the core transistor. The technique is verified with simulations and implemented in a prototype 2.4 GHz PA for WLAN application. The PA is fabricated in a 0.35-mum CMOS and achieves a small-signal gain of 25.4 dB, output P1dB of 25.1 dBm, and a power-added efficiency (PAE) of 40%.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357898","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
A biasing scheme that improves the linearity of linear mode power amplifiers (PA) is presented. This technique employs adding feedback to a current mirror bias to enhance the linearity of the amplifier by compensating the nonlinear input capacitance of the core transistor. The technique is verified with simulations and implemented in a prototype 2.4 GHz PA for WLAN application. The PA is fabricated in a 0.35-mum CMOS and achieves a small-signal gain of 25.4 dB, output P1dB of 25.1 dBm, and a power-added efficiency (PAE) of 40%.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
