W. Blake, P. English, N. Forrester, T. Furlong, R. Rose, R. Watson
{"title":"A VLSI chip set for an integrated text and graphics video subsystem","authors":"W. Blake, P. English, N. Forrester, T. Furlong, R. Rose, R. Watson","doi":"10.1109/ISSCC.1986.1156992","DOIUrl":null,"url":null,"abstract":"A chip set for a 1024×864 pixel, 60Hz non-interlaced display will be reported. The set allows simultaneous display of text and graphics at throughput rates of 20,000-characters per second and 8-million pixels per second, respectively. Features include smooth scrolling, clipping, scaling and rotation. In 3.5μm NMOS, typical power dissipation is 2W per chip.","PeriodicalId":440688,"journal":{"name":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1986.1156992","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract
A chip set for a 1024×864 pixel, 60Hz non-interlaced display will be reported. The set allows simultaneous display of text and graphics at throughput rates of 20,000-characters per second and 8-million pixels per second, respectively. Features include smooth scrolling, clipping, scaling and rotation. In 3.5μm NMOS, typical power dissipation is 2W per chip.
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