Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults

Abstract

Diagnostic self-test in-the-field for processors becomes mandatory for reconfigurable fault tolerant processor-based systems. Software-based self-test techniques are well suited for providing a pass/fail test in-the-field. However, a diagnostic result for dynamically scheduled processors is usually not obtained by these tests, because the software has no control about the used components of the processor during the execution of the test program. This paper provides a concept for a simple hardware extension of a dynamically scheduled processor, such that the test program gets control about the resource usage. With this technique, for the first time, it becomes feasible to perform a diagnostic software-based self-test for dynamically scheduled processors that is able to distinguish between faults in various components of the processor. In particular, the instruction queue, reservation stations, functional units, and reorder buffer are taken into account. Thereby, the hardware overhead for self-test and reconfiguration is less than 6%.