M. Hashizume, H. Yotsuyanagi, M. Ichimiya, T. Tamesada, M. Takeda
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引用次数: 9
Abstract
A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.
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