Mismatch compensation in low power operational transconductance amplifiers using MIFGMOS

Abstract

The present trend on VLSI CMOS technology is to reduce the transistor switching losses by reducing the supply voltage and increasing the operational frequency, at the cost of increasing the non-idealities on the transistors. For mixed mode applications, the analog engineer must cope with these issues to design analog-to-digital converters or analog applications using nanometric CMOS devices. In this paper, a design approach based on a multiple input floating gate technology is applied to a fully differential low power, low voltage operational transconductance amplifier that allows the use of low supply voltages and reduces the mismatch of the transistors. Simulation results indicate that the use of the floating gate approach does not show any advantage to control the gain of the amplifier. However, this approach is very useful as a means to control the differential pair voltage of the proposed design, allowing an offset voltage compensation of nearly zero volts. The performance of the proposed design approach is demonstrated by considering a voltage supply bias of +/− 0.45V, by obtaining a dissipated power of 12.2 microwatts, a bandwidth of 120 kHz, and 35 dB gain. The design is performed using the Cadence design framework environment based on a 130nm technology.