An Efficient CMOS Dynamic Logic-Based Full Adder

Abstract

In this paper, a new topology for dynamic logic-based full adder is proposed and analyzed. The XOR and XNOR gates are generally used as basic logic blocks in the full adder design. In this work, the modified architectures of XOR and XNOR logic gates are used in the implementation of full adder circuit. The suggested topology of XOR/XNOR gates exhibits a full logic swing. The proposed full adder circuit is simulated using the conventional 180 nm CMOS process technology. The simulation results using SPICE simulation tool demonstrate that there are substantial improvements in power dissipation and speed of the proposed circuit compared to the earlier reported designs.