[2009] An Instruction Decomposition Method for Reconfigurable Decoders

Abstract

Embedded multimedia processors are required to execute many kinds of traditional instruction sets. Since decomposition and translation of instructions by software emulators have larger overhead than that by hardware units, an IPC on software emulators is lower than that on real processors. In this paper, we propose a new method for executing many kinds of traditional instruction sets. The method decomposes them into internal instructions based on information from memory. The memory-based decoder decomposes target CISC instructions into simple instructions. We evaluate an instruction decomposition method and the memory-based decoders. The average IPC of a memory-based decoder is 0.53, which is six times higher than that on JIT type software emulators. The total memory size of the decoder is 98 KB. The chip area of the processor that has the decoder using RAM is 1.36 times larger than that with a hardwired decoder. Therefore, we conclude that the proposed method provides a good tradeoff between chip area and performance.