A calibration architecture for improving the performance of time-interleaved ADC

Abstract

A well known problem of time-interleaved analog-to-digital converters is the matching between the channels of the converter. The random mismatch of components between the channels affects the accuracy of the converter especially for high-resolution converters. In this paper, a digital self-calibration is proposed based on least mean square (LMS) algorithm for canceling the offset and gain mismatches. And a global sampling clock using feed-forward compensates for the bottom-plate sampling skew. Simulations on the four-channel time-interleaved pipelined ADC shows that after calibration, the converter could attain 10-bit accuracy successfully.