Applying testability to an ASIC architectural core

Proceedings., Second Annual IEEE ASIC Seminar and Exhibit, Pub Date : 1989-09-25 DOI:10.1109/ASIC.1989.123192

J. Couleur, S. Cravatta

引用次数: 3

Abstract

The device-level testing of an application-specific integrated circuit (ASIC) that is designed using VLSI cores and LSI peripheral cells is discussed. The Intel ASIC UCS51 microcontroller product family is described, and the UCS51 test methodology is compared to that of the Intel standard product 80C51. A solution that provides the ASIC customer with a flexible design environment without compromising device testing is accomplished by employing built-in test modes, which are designed into the microcontroller core and accessed through a minimal amount of device package pins.<>

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将可测试性应用于ASIC架构核心

讨论了用VLSI内核和LSI外围单元设计的专用集成电路(ASIC)的器件级测试。描述了英特尔ASIC UCS51微控制器产品系列，并将UCS51测试方法与英特尔标准产品80C51进行了比较。通过采用内置测试模式，为ASIC客户提供灵活的设计环境，而不影响设备测试，该解决方案被设计到微控制器核心中，并通过最少量的设备封装引脚进行访问。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,

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